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CD4031BMS
December 1992
CMOS 64-Stage Static Shift Register
Description
The CD4031BMS is a static shift register that contains 64 Dtype, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage). The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 12MHz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The CD4031BMS has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation. Alternatively, a delayed clock output (CLD) is provided that enables cascading register packages while allowing reduced clock drive fan-out and transition-time requirements. A third cascading option makes use of the Q' output from the 1/2 stage, which is available on the next negative-going transition of the clock after the Q output occurs. This delayed output, like the delayed clock CLD, is used with clocks having slow rise and fall times. The CD4031BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W
Features
* High Voltage Type (20V Rating) * Fully Static Operation: DC to 12MHz (typ.) at VDD VSS = 15V * Standard TTL Drive Capability on Q Output * Recirculation Capability * Three Cascading Modes: - Direct Clocking for High-Speed Operation - Delayed Clocking for Reduced Clock Drive Requirements - Additional 1/2 Stage for Slow Clocks * 100% Tested For Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Serial Shift Registers * Time Delay Circuits
Pinout
CD4031BMS TOP VIEW
RECIRCULATE DATA IN 2 1 CLOCK INHIBIT 2 NC 3 NC 4 Q' 5 Q6 Q7 VSS 8 NC = NO CONNECTION
Functional Diagram
DATA 1 15 IN MODE 10 CONT. RECIRC DATA 2 IN CLOCK IN 1 CONTROL LOGIC 64 STAGES DATA OUT 6 DATA OUT 7
16 VDD 15 DATA IN 1 14 NC 13 NC 12 NC 11 NC 10 MODE CONTROL 9 CLD
2
CL CLOCK LOGIC CL
VDD = 16 VSS = 8 NC = 3, 4, 11, 12, 13, 14
9 DELAYED CLOCK OUT
1/2 STAGE
Q' 5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3306
7-816
Specifications CD4031BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current Q, Q', CLD VOL15 VOH15 IOL5 IOL10 IOL15 Output Current Q Output Current Q Output Current Q Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC
o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 0.51 1.3 3.4 2.04 5.2 13.6 -2.8 0.7
MAX 10 1000 10 100 1000 100 50 -0.51 -1.6 -1.3 -3.4 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA mA mA mA V V V
+25oC, +125oC, -55oC 14.95
VOH > VOL < VDD/2 VDD/2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-817
Specifications CD4031BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPHL2 VDD = 5V, VIN = VDD or GND 9 10, 11 TPLH3 TPHL3 TPHL4 TPLH4 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 2 1.48 MAX 500 675 500 675 380 513 380 513 200 270 200 270 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Q Propagation Delay Clock to Q Propagation Delay Clock to Q Propagation Delay Clock to Q' Propagation Delay Clock to CLD Transition Time
SYMBOL TPHL1 TPLH1 TPLH2
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
Maximum Clock Input Frequency (See Note 5; Table 3) NOTES:
+25oC +125oC, -55oC
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Q, Q', CLD Outputs Output Current (Sink) Q, Q', CLD Outputs Output Current (Sink) Q, Q', CLD Outputs Output Current (Sink) Q Outputs VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 1.44 2.56 50 mV V V mA mA mA mA mA mA mA mA
o o
MIN -
MAX 5 150 10 300 10 600 50
UNITS A A A A A A mV
7-818
Specifications CD4031BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) Q Outputs Output Current (Sink) Q Outputs Output Current (Source) SYMBOL IOL10 CONDITIONS VDD = 10V, VOUT = 0.5V NOTES 1, 2 TEMPERATURE +125oC -55 C IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55 IOH5A VDD = 5V, VOUT = 4.6V 1, 2
oC o
MIN 3.6 6.4 9.6 16.8 -
MAX -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 220 180 220 180 160 130 100 80 160 130 100 80 5 6 1000 1000 200 60 30 20 60 30 20 240 100 80 7.5
UNITS mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz s s s ns ns ns ns ns ns ns ns ns pF
+125oC -55oC +125oC -55o C +125oC -55
oC
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125oC -55 C
o
Input Voltage Low Input Voltage High Propagation Delay Clock to Q Propagation Delay Clock to Q Propagation Delay Clock to Q Propagation Delay Clock to CLD Propagation Delay Clock to Q' Transition Time
VIL VIH TPHL1 TPLH1 TPLH2
VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V
1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2
+25o
C, +125 C, -55oC
o
+7 -
+25oC, +125oC, -55oC +25oC +25
oC
+25oC +25 C +25
oC o
TPHL2
VDD = 10V VDD = 15V
+25oC +25
oC
TPLH3 TPHL3 TPLH4 TPHL4 TTHL TTLH FCL
VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V
+25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
Maximum Clock Input Frequency (Note 5) Clock Input Rise or Fall Time (Note 4)
TRCL TFCL
VDD = 5V VDD = 10V VDD = 15V
Minimum Data Setup Time
TS
VDD = 5V VDD = 10V VDD = 15V
Minimum Data Hold Time
TH
VDD = 5V VDD = 10V VDD = 15V
Minimum Clock Pulse Width
TW
VDD = 5V VDD = 10V VDD = 15V
Input Capacitance
CIN
Any Input
7-819
Specifications CD4031BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded in the parallel clocked application, TRCL should be made the sum of the propagation delay at 50pF and the transition time of the output driving stage. 5. Maximum clock frequency for cascaded units; a) Using Delayed Clock feature in recirculation mode: 1 FMAX = ------------------------------------------------------------------------------------------------------------------------------------- where n = number of packages ( n-1 ) CL, prop delay and Q prop delay and set - up time b) Not using Delayed Clock: 1 FMAX = ---------------------------------------------------------------------------propagation delay and set - up time SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VNTH VPTH VPTH F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V (Worst Case) 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. VDD = 5V, CL = 50pF, RL = 200K 3. See Table 2 for +25oC limit. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) SYMBOL IDD IOL5 1.0A 20% x Pre-Test Reading DELTA LIMIT
7-820
Specifications CD4031BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Output Current (Source) SYMBOL IOH5A DELTA LIMIT 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 3 - 7, 9, 11 - 14 3 - 7, 9, 11 - 14 3 - 5, 11 - 14 3 - 7, 9, 11 - 14 GROUND 1, 2, 8, 10, 15 8 8, 15 8 VDD 16 1, 2, 10, 15, 16 1, 16 1, 2, 10, 15, 16 6, 7, 9 2 10 9V -0.5V 50kHz 25kHz
7-821
CD4031BMS Logic Diagram
CL CL
*
15 DATA 1 IN p n CL CL p n 63 IDENTICAL STAGES CL p n p n CL
*
10 MODE CONTROL
*
1 RECIRCULATE (DATA 2 IN) CL
CL
CL
CL
p
p n CL CL CL p p n
*
2 CLOCK 9 CLD CL
n
CL
n
CL
CL CL
CL
p VDD n CL *ALL INPUTS ARE PROTECTED BY CMOS/MOS PROTECTION NETWORK CL p n 5 VSS CL Q' 7 Q 6 Q
INPUT CONTROL CIRCUIT TRUTH TABLE BIT INTO STAGE 1 1
TYPICAL STAGE TRUTH TABLE DATA 0 CL DATA + 1
TRUTH TABLE FOR OUTPUT FROM Q' (TERMINAL 5) DATA + 64 1/2 0 1 NC 0 = Low Level NC = No Change
DATA 1 0 X X
RECIR X X 1 0
MODE 0 0 1 1
DATA + 64 0 0 1 1 1 X NC X 1 = High Level X = Don't Care 0 = Low Level NC = No Change 1 = High Level X = Don't Care
CL
0 1 0
1 = High Level X = Don't Care
0 = Low Level NC = No Change
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
822
CD4031BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1 . TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS (Q SINK CURRENT = 4X ORDINATE)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS (Q SINK CURRENT = 4X ORDINATE)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (SEE TABLE) AMBIENT TEMPERATURE (TA) = +25oC tPHL, tPLN - CLOCK TO Q tPLH - CLOCK TO Q 300 SUPPLY VOLTAGE (VDD) = 5V
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (SEE TABLE) AMBIENT TEMPERATURE (TA) = +25oC tPHL, tPLN - CLOCK TO Q tPLH - CLOCK TO Q 300
SUPPLY VOLTAGE (VDD) = 5V 200
200 10V 100 15V
100
10V 15V
0
20
60 80 40 LOAD CAPACITANCE (CL) (pF)
100
0
20
60 80 40 LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (SEE TABLE)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (SEE TABLE)
7-823
CD4031BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) TRANSITION TIME (tTHL) (ns)
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
75 SUPPLY VOLTAGE (VDD) = 5V 50
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
10V 25 15V
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
0
20
40 60 80 LOAD CAPACITANCE (CL) (pF)
100
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE (EXCEPT Q, tTHL)
8 6 4 2
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE (Q, tTHL)
POWER DISSIPATION PER (PD) (W)
10K
8 6 4 2
SUPPLY VOLTAGE (VDD) = 15V
1K
8 6 4 2
10V 10V 5V CL = 50pF CL = 15pF AMBIENT TEMPERATURE (TA) = +25oC
2 4 68 2 4 68 2 4 68 2 4 68
100
8 6 4 2
10 10 100 1K CLOCK INPUT FREQUENCY (fCL) (kHz) 10K
FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY
VDD DATA 15 MODE CONTROL RECIRC IN 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 6 Q D 15 6 Q D 15 6 Q D 15 6 Q
CLOCK DRIVER MODE CONTROL VDD = RECIRCULATION GND = NEW DATA
FIGURE 10. CASCADING USING DIRECT CLOCKING FOR HIGH-SPEED OPERATION (SEE CLOCK RISE AND FALL TIME REQUIREMENT)
7-824
CD4031BMS
VDD DATA 15 MODE CONTROL RECIRC IN 10 CD4031BMS 1 9 CLD 2 CL 10 CD4031BMS 1 9 CLD 2 CL 10 CD4031BMS 1 9 CLD 2 CL 10 CD4031BMS 1 9 2 CLD CL CLOCK DRIVER (1/2 - CD4013B) DELAYED CLOCK TO CLOCK NEW DATA INTO FIRST REGISTER D FF* CL Q 6 Q D 15 6 Q D 15 6 Q D 15 6 Q
*FOR RECIRCULATION MODE ONLY
FF TO DELAY DATA UNTIL FISRT REGISTERED DELAYED CLOCKING HAS OCCURED
MODE CONTROL VDD = RECIRCULATION GND = NEW DATA
FIGURE 11. CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS
VDD DATA 15 MODE CONTROL RECIRC IN 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 10 CD4031BMS 1 2 CL 6 5 Q' D 15 5 Q' D 15 5 Q' D 15 5 Q'
CLOCK DRIVER MODE CONTROL VDD = RECIRCULATION GND = NEW DATA
FIGURE 12. CASCADING USING HALF-CLOCK-PULSE DELAYED OUTPUT (Q') TO PERMIT USE OF SLOW RISE AND FALL CLOCK INPUTS
Chip Dimensions and Pad Layout
METALLIZATION: Thickness: 11kA - 14kA, AL. PASSIVATION: 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
7-825

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